CPU Cache-Friendly Data Structures in Go: 10x Speed with Same Algorithm
skoredin.pro·1h·
Discuss: Hacker News
⚡Cache Optimization
Rigorous Evaluation of Microarchitectural Side-Channels with Statistical Model Checking
arxiv.org·4h
📱Bytecode Design
A Primer on Memory Consistency and Cache Coherence, Second Edition
link.springer.com·14h·
Discuss: r/programming
🧠Memory Models
Why We Need SIMD
parallelprogrammer.substack.com·5h·
Discuss: Substack
🔀SIMD Programming
Beyond Von Neumann: Toward a unified deterministic architecture
venturebeat.com·1d
🤝Cooperative Threading
1GHz Renesas RA8T2 Cortex-M85 MCUs feature MRAM and EtherCAT for industrial motor control
cnx-software.com·7h
🔌Microcontrollers
Intel Core Ultra X9/X7/X5 "Panther Lake-H" and "Panther Lake-U" Configurations Leak
techpowerup.com·3h
🔧RISC-V
Understanding the KV Cache (feat. Self-Attention)
dev.to·1h·
Discuss: DEV
🔄Subinterpreters
Multiply kernels on one system.
reddit.com·15h·
Discuss: r/linux
🌱Forth Kernels
A gentle introduction to GEMM using MMA tensor cores
am17an.bearblog.dev·3d·
Discuss: Hacker News
📏Linear Memory
Your RAM has more than one XMP profile, and here's when to use the others
xda-developers.com·1d
⚡Performance
Highly concurrent in-memory counter in GoLang
engineering.grab.com·8h
🧠Memory Models
Leaker Clears The Air On Intel Core Ultra X Series, Models To Feature Full Xe3 iGPU
pokde.net·14h
🔧RISC-V
The Role of AI in Next-Gen Chip Design
dev.to·8h·
Discuss: DEV
🔌Microcontrollers
How we trained an ML model to detect DLL hijacking
securelist.com·20m
🏷️Memory Tagging
LLM-Based Instance-Driven Heuristic Bias in the Context of a BRKGA
researchgate.net·1d·
Discuss: Hacker News
🪜Recursive Descent
Why Intel Rallied in September
fool.com·14h
🔧RISC-V
The Future is Composable: Orchestrating Multiple APIs with FastServe MCP Servers
dev.to·18h·
Discuss: DEV
🌉Language Bridges
XiangShan Vector Floating-Point Unit Design
docs.xiangshan.cc·1d·
Discuss: Hacker News
🎯Bit Vectors
Measuring Reorder Buffer Capacity
blog.stuffedcow.net·3d·
Discuss: Lobsters, Hacker News
📝Register Allocation